Semi-Amorphized Channel Engineering to Suppress the Parasitic BJT Effect in Next-Generation 4F² DRAM : 차세대 4F² DRAM의 기생 BJT 효과 억제를 위한 부분비정질화 채널 구조 설계
차세대 4F² DRAM의 기생 BJT 효과 억제를 위한 부분 비정질화 채널 구조 설계
- 발행기관 강원대학교 일반대학원
- 지도교수 도움말 Myung-Hyun Baek
- 발행년도 2026
- 학위수여년월 2026. 6
- 학위명 석사
- 학과 및 전공 도움말 일반대학원 전자공학과（강릉）
- 세부분야 해당없음
- 실제URI http://www.dcollection.net/handler/kangnung/000000012511
- UCI I804:42001-000000012511
- 본문언어 영어
초록/요약 도움말
Scaling of dynamic random access memory （DRAM） technology below the 10 nm era has pushed the conventional 6F² buried channel array transistor （BCAT） cell structure toward a set of compounding limits, among them intensifying short-channel effects, stronger electrical interference between neighboring cells, and growing difficulty integrating capacitor fabrication processes that demand increasingly high aspect ratios. The 4F² vertical channel array transistor （VCAT） DRAM has drawn growing attention as a next-generation, high-density structure able to ease these difficulties. Separating the bit line （BL） and storage node （SN） along the vertical direction allows VCAT to shrink the planar cell area down to 4F². VCAT, however, has no body contact, and this floating-body configuration leaves holes generated by gate-induced drain leakage （GIDL） free to collect inside the channel. Once enough charge has accumulated, the channel barrier drops and the parasitic bipolar junction transistor （BJT） effect turns on, so that the stored Data '1' state can be lost well before the next access, a condition referred to as retention failure. This thesis investigates the physical origin of Data '1' retention failure in 4F² VCAT DRAM and presents a device structure designed to suppress it. Using technology computer-aided design （TCAD） simulation, the retention characteristics of conventional BCAT, double-gate VCAT （DG-VCAT） , and gate-all-around VCAT （GAA-VCAT） wascompared under matched bias conditions. A quantitative read failure threshold tied to the storage-node voltage （SNV） was also established by accounting for the mismatch behavior of the bit-line sense amplifier （BLSA）. The analysis showed that, unlike BCAT, whose body contact stays functional, GIDL-generated holes pile up inside the floating body of both DG-VCAT and GAA-VCAT, opening a path for parasitic BJT current to flow. Junction engineering together with an asymmetric back-gate （BG） structure brought partial relief, lowering GIDL and extending the retention time, but stopped short of removing the floating-body-driven BJT activation altogether. To overcome this remaining limitation, the semi-amorphized GAA-VCAT （SAGAA-VCAT） is proposed in this thesis, with a semi-amorphized region （SAR） selectively placed inside the silicon channel by means of pre-amorphization implant （PAI）. This approach calls for no extra epitaxial growth step and can be carried out using ion implantation alone, while the trap states formed within the SAR encourage the capture and recombination of carriers moving along the parasitic BJT current path. As a result, the parasitic BJT current that would otherwise grow once the floating body becomes charged is held in check. With an SAR radius of 4 nm, TCAD results showed the parasitic BJT current falling by close to 93.8% relative to the conventional GAA-VCAT, while the accompanying drop in on-current stayed within 5.62%. Consequently, the Data '1' retention time climbed to roughly 260 ms, well above the 64 ms refresh interval set by JEDEC. Based on these simulation outcomes, the proposed SAGAA-VCAT structure stands out as a promising route toward improving the retention reliability of next-generation 4F² VCAT DRAM.
more목차 도움말
Ⅰ. Introduction 1
1. Paradigm Shift from 6F² BCAT DRAM to 4F² VCAT DRAM 1
2. Data '1' Failure Mechanisms in 4F² VCAT DRAM 4
1） Gate-Induced Drain Leakage（GIDL） 4
2） Floating Body Effect （FBE） 6
3） Parasitic BJT Effect 7
Ⅱ. TCAD Simulation Methodology 9
1. Device Structures and Simulation Setup 9
2. Bias Conditions and Operation Scheme 12
3. Numerical Definition of the Read Failure Criterion 14
Ⅲ. Double-Gate VCAT DRAM 18
1. Electrical and Refresh Characteristics of BCAT and DG-VCAT 18
2. Physical Analysis of Data '1' Retention Failure Mechanism 21
3. Device Optimization for Retention time Enhancement 27
Ⅳ. Gate-All-Around VCAT DRAM 35
1. Characteristics of GAA-VCAT 35
2. Proposed Device Structure with a Semi-Amorphized Region 37
3. Fabrication Process Flow 39
4. Device Performance of the Semi-Amorphized GAA-VCAT 41
Ⅴ. Conclusion 45
Reference 47
Abstract 51
감사의 글 53
