| 항목 | Soms Field | 내용 | 언어 |
|---|---|---|---|
| 제목 | dc.title | 듀얼모드를 이용한 64비트 Fused Multiply-Add 연산의 구현 | |
| 제목(제2언어) | somsterms.translated | Implementation of a 64-Bit Fused Multiply-Add Operation Using Dual Mode | |
| 저자 | dc.creator | 申盛旭 | |
| 저자(제2언어) | somsterms.otherName | Shin, Seongwook | |
| 소속 | somsterms.affiliation | 江陵大學校 大學院 | |
| 발행기관 | dc.publisher | 江陵大學校 大學院 | |
| 지도교수 | somsterms.advisor | 전덕수 | |
| 발행년도 | dcterms.issued | 2008 | |
| 학위수여년월 | somsterms.awarded | 2008. 2 | |
| 자료유형 | somsterms.subType | 학위논문 | |
| 학위명 | somsterms.thesisDegree | 석사 | |
| 학과 및 전공 | somsterms.major | 電子工學科 | |
| 원문형식 | dc.format | application/pdf | |
| 원문크기 | dcterms.extent | 967305 bytes | |
| 원문매체 | dcterms.medium | application/pdf | |
| 원문페이지 | somsterms.page | iii, 45 p. | |
| 본문언어 | dc.language | 한국어 | |
| 초록/요약 | dcterms.abstract |
This thesis is about an Implementation of a 64-Bit Fused Multiply-Add Operation. A FMA (Fused Multiply-Add) operation combines a multiply operation and add operation, and it does the multiply and add operation simultaneously. For the high-speed FMA operation, Dual Mode is used. The Dual Mode means that one function is divided into two and the two divided parts are operated simultaneously. The multiply operation is composed of a divide and a conquer mode. In the divide mode, partial products are made by a 13 x 13 Radix-4 Booth Recording and calculated by a Wallace Tree in the conquer mode. The add operation is made of a sum and sum+1 modes. The sum and sum+1 modes compute the value of carry in = `0' and carry in =`1' cases, respectively, and are selected by the values of carry in. A FPGA (XC4VLX25) is used to prototype the FMA operation which is modeled by VHDL. Both results of functional and timing simulation show that the FMA operation works well. The multiply operation didn't cut the work-time down because of the increased logic level, but the add operation cut it down half. |
영어 |
| 목차 | dcterms.tableOfContents |
1 서론 = 1
2 IEEE 표준 745의 개요 = 3 2.1 수의 부호화 = 3 2.2 반올림 방식 = 7 2.3 Exceptions = 7 3 덧셈기와 곱셈기의 Dual-Mode 구조 = 9 3.1 부동 수수점 가산 알고리즘 = 9 3.1.1 General Adder = 9 3.1.2 Brent-Kung Adder = 10 3.2 부동 소수점 승산 알고리즘 = 13 3.2.1 Karatsuba's Divide and Conquer Algorithm = 13 3.2.2 Radix-4 Booth Algorithm = 15 3.2.3 Wallace Tree = 18 4 Fused Multiply-Add 구조 = 21 4.1 FMA 연산 명령어의 Data Flow = 21 4.2 53 x 53 Bit Multiplier = 23 4.2.1 Division = 23 4.2.2 13 x 13 Radix-4 Booth Multiplier = 25 4.2.3 Conquest = 25 4.3 161-Bit Alignment Shifter = 29 4.4 161-Bit Adder = 30 4.5 Leading Non-Zero Detector = 32 4.6 Normalization Shifter = 35 5 구현 및 검증 = 36 5.1 FMA Top Module = 36 5.2 53 x 53 Bit Multiplier = 40 5.3 161-Bit Adder = 41 5.4 FPGA 구현 = 43 6 결론 = 45 |